RISC-V Architecture and DSP Processor by Zhang Zhiwei (.PDF)

File Size: 29.7 MB

RISC-V Architecture and DSP Processor Design: Design and implement a high-performance RISC-V DSP core from ISA to SoC by Zhang Zhiwei
Requirements: .PDF reader, 29.7 MB
Overview: Dive into the practical design of a high-performance RISC-V DSP core with this hands-on guide. Using the SpringCore architecture as a case study, it walks through custom ISA extensions, an 8-stage pipeline, and real-time control features, all the way to the final SoC implementation. The book also covers the full software ecosystem, including an LLVM toolchain and Eclipse-based debugging, bridging the gap from hardware architecture to a working 150 MHz DSP chip.
Genre: Non-Fiction > Tech & Devices

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https://rapidgator.net/file/d501b4be931becf47839ba2e96b9834c